NDS Registers

Important Registers

Todo:

complete register documentation

(A00) determine what happens when two backgrounds have the same priority.

(A00) document mosaic background bit.

(A00) enhance documentation after providing background demo.

(A00) enhance documentation after using a map larger than the screen.

(A00) verify that text backgrounds can't wrap.

determine tile offset vs. pixel offset. If pixel offset, change background sizes above to pixels rather than tiles, or put the tile sizes in parenthesis.

(A00) determine what happens when two backgrounds have the same priority.

(A00) document mosaic background bit.

(A00) enhance documentation after providing background demo.

(A00) enhance documentation after using a map larger than the screen.

(A00) verify that text backgrounds can't wrap.

BG0_CR (0x04000008)	BG1_CR (0x0400000A)	BG2_CR (0x0400000C)
BG3_CR (0x0x0400000E)	DISP_SR	DISPLAY_CR (0x04000000)
IE	IF	IME
IRQ_HANDLER	POWER_CR	SUB_BG0_CR (0x04001008)
SUB_BG1_CR (0x0400100A)	SUB_BG2_CR (0x0400100C)	SUB_BG3_CR (0x0400100E)
SUB_DISPLAY_CR (0x04001000)	VRAM_A_CR (0x04000240)	VRAM_B_CR (0x04000241)
VRAM_C_CR (0x04000242)	VRAM_D_CR (0x04000243)	VRAM_E_CR (0x04000244)
VRAM_F_CR (0x04000245)	VRAM_G_CR (0x04000246)	VRAM_H_CR (0x04000247)
VRAM_I_CR (0x04000248)	BG0_X0 (0x04000010)	BG0_Y0 (0x04000012)
BG1_X0 (0x04000014)	BG1_Y0 (0x04000016)	BG2_X0 (0x04000018)
BG2_Y0 (0x0400001A)	BG3_X0 (0x0400001C)	BG3_Y0 (0x0400001E)
SUB_BG0_X0 (0x04001010)	SUB_BG0_Y0 (0x04001012)	SUB_BG1_X0 (0x04001014)
SUB_BG1_Y0 (0x04001016)	SUB_BG2_X0 (0x04001018)	SUB_BG2_Y0 (0x0400101A)
SUB_BG3_X0 (0x0400101C)	SUB_BG3_Y0 (0x0400101E)	BG2_XDX (0x04000020)
BG2_XDY (0x04000022)	BG2_YDX (0x04000024)	BG2_YDY (0x04000026)
BG2_CX (0x04000028)	BG2_CY 0x0400002C)	BG3_XDX (0x04000030)
BG3_XDY (0x04000032)	BG3_YDX (0x04000034)	BG3_YDY (0x04000036)
BG3_CX (0x04000038)	BG3_CY (0x0400003C)	SCHANNEL_CR(0) (0x04000400)
SCHANNEL_SOURCE(0) (0x04000404)	SCHANNEL_TIMER(0) (0x04000408)	SCHANNEL_REPEAT_POINT(0) (0x0400040A)
SCHANNEL_LENGTH(0) (0x0400040C)	SCHANNEL_CR(1) (0x04000410)	SCHANNEL_SOURCE(1) (0x04000414)
SCHANNEL_TIMER(1) (0x04000418)	SCHANNEL_REPEAT_POINT(1) (0x0400041A)	SCHANNEL_LENGTH(1) (0x0400041C)
SCHANNEL_CR(2) (0x04000420)	SCHANNEL_SOURCE(2) (0x04000424)	SCHANNEL_TIMER(2) (0x04000428)
SCHANNEL_REPEAT_POINT(2) (0x0400042A)	SCHANNEL_LENGTH(2) (0x0400042C)	SCHANNEL_CR(3) (0x04000430)
SCHANNEL_SOURCE(3) (0x04000434)	SCHANNEL_TIMER(3) (0x04000438)	SCHANNEL_REPEAT_POINT(3) (0x0400043A)
SCHANNEL_LENGTH(3) (0x0400043C)	SCHANNEL_CR(4) (0x04000440)	SCHANNEL_SOURCE(4) (0x04000444)
SCHANNEL_TIMER(4) (0x04000448)	SCHANNEL_REPEAT_POINT(4) (0x0400044A)	SCHANNEL_LENGTH(4) (0x0400044C)
SCHANNEL_CR(5) (0x04000450)	SCHANNEL_SOURCE(5) (0x04000454)	SCHANNEL_TIMER(5) (0x04000458)
SCHANNEL_REPEAT_POINT(5) (0x0400045A)	SCHANNEL_LENGTH(5) (0x0400045C)	SCHANNEL_CR(6) (0x04000460)
SCHANNEL_SOURCE(6) (0x04000464)	SCHANNEL_TIMER(6) (0x04000468)	SCHANNEL_REPEAT_POINT(6) (0x0400046A)
SCHANNEL_LENGTH(6) (0x0400046C)	SCHANNEL_CR(7) (0x04000470)	SCHANNEL_SOURCE(7) (0x04000474)
SCHANNEL_TIMER(7) (0x04000478)	SCHANNEL_REPEAT_POINT(7) (0x0400047A)	SCHANNEL_LENGTH(7) (0x0400047C)
SCHANNEL_CR(8) (0x04000480)	SCHANNEL_SOURCE(8) (0x04000484)	SCHANNEL_TIMER(8) (0x04000488)
SCHANNEL_REPEAT_POINT(8) (0x0400048A)	SCHANNEL_LENGTH(8) (0x0400048C)	SCHANNEL_CR(9) (0x04000490)
SCHANNEL_SOURCE(9) (0x04000494)	SCHANNEL_TIMER(9) (0x04000498)	SCHANNEL_REPEAT_POINT(9) (0x0400049A)
SCHANNEL_LENGTH(9) (0x0400049C)	SCHANNEL_CR(10) (0x040004A0)	SCHANNEL_SOURCE(10) (0x040004A4)
SCHANNEL_TIMER(10) (0x040004A8)	SCHANNEL_REPEAT_POINT(10) (0x040004AA)	SCHANNEL_LENGTH(10) (0x040004AC)
SCHANNEL_CR(11) (0x040004B0)	SCHANNEL_SOURCE(11) (0x040004B4)	SCHANNEL_TIMER(11) (0x040004B8)
SCHANNEL_REPEAT_POINT(11) (0x040004BA)	SCHANNEL_LENGTH(11) (0x040004BC)	SCHANNEL_CR(12) (0x040004C0)
SCHANNEL_SOURCE(12) (0x040004C4)	SCHANNEL_TIMER(12) (0x040004C8)	SCHANNEL_REPEAT_POINT(12) (0x040004CA)
SCHANNEL_LENGTH(12) (0x040004CC)	SCHANNEL_CR(13) (0x040004D0)	SCHANNEL_SOURCE(13) (0x040004D4)
SCHANNEL_TIMER(13) (0x040004D8)	SCHANNEL_REPEAT_POINT(13) (0x040004DA)	SCHANNEL_LENGTH(13) (0x040004DC)
SCHANNEL_CR(14) (0x040004E0)	SCHANNEL_SOURCE(14) (0x040004E4)	SCHANNEL_TIMER(14) (0x040004E8)
SCHANNEL_REPEAT_POINT(14) (0x040004EA)	SCHANNEL_LENGTH(14) (0x040004EC)	SCHANNEL_CR(15) (0x040004F0)
SCHANNEL_SOURCE(15) (0x040004F4)	SCHANNEL_TIMER(15) (0x040004F8)	SCHANNEL_REPEAT_POINT(15) (0x040004FA)
SCHANNEL_LENGTH(15) (0x040004FC)

POWER_CR

VRAM_A_CR (0x04000240)

VRAM_B_CR (0x04000241)

VRAM_C_CR (0x04000242)

VRAM_D_CR (0x04000243)

VRAM_E_CR (0x04000244)

VRAM_F_CR (0x04000245)

VRAM_G_CR (0x04000246)

VRAM_H_CR (0x04000247)

VRAM_I_CR (0x04000248)

DISPLAY_CR (0x04000000)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
31	BGExtPal	29	28	27	26	25	24	23	22	21	20	FBBank		ExtMode
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SprWin	Win1	Win0	Obj	BG3	BG2	BG1	BG0	BlnkScr	U6	OAMHorzBlank	ObjMapMode	3D	Mode

• Mode -- Screen Mode (ignored unless ExtMode is set to 1.) --
• 3D --
• ObjMapMode -- Object Mapping Mode -- This bit specifies the layout of sprite graphics. When set to 0, it specifies that the objects are stored in 1D mode. When set to 1, it speicifes that the objects are stored in 2D mode. See Sprite Mapping Modes for detailed information about the modes.
• OAMHorzBlank -- OAM Access during Horizontal Blank -- When set to 1, it allows the application to update the OAM during the horizontal blank of the video being drawn. When set to 0, access to the OAM by the application is prevented.
• U6 -- Functionality of this bit is unknown.
• BlnkScr -- Blank Screen -- When set to zero, the screen behaves normally. When set to 1, this bit causes the screen to blank and go white.
• BG0 -- Background #0 Active -- When set to zero, Background #0 is not active. When set to 1, Background #0 becomes active (BG0_CR (0x04000008).)
• BG1 -- Background #1 Active -- When set to zero, Background #1 is not active. When set to 1, Background #1 becomes active (BG1_CR (0x0400000A).)
• BG2 -- Background #2 Active -- When set to zero, Background #2 is not active. When set to 1, Background #2 becomes active (BG2_CR (0x0400000C).)
• BG3 -- Background #3 Active -- When set to zero, Background #3 is not active. When set to 1, Background #3 becomes active (BG3_CR (0x0x0400000E).)
• Obj -- Sprite Objects Active --
• Win0 --
• Win1 --
• SprWin --
• ExtMode -- Extended Mode setting -- These two bits control
• FBBank -- Frame Buffer Mode --
• BGExtPal --

SUB_DISPLAY_CR (0x04001000)

BG0_CR (0x04000008)

This 16 bit register controls the features related to background #0 on the main display. To activate this register, this background must be enabled in the DISPLAY_CR (0x04000000).

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Size		Wrap	Map					Color	Mosaic	Tile				Pri

• Pri -- Priority -- This determines the priority level of the background. 0 is the hightest priority and will be the top most layer of the backgrounds and drawn on top of all the other layers. 3 is the lowest priority. When a sprite and a layer have the same priority, the sprite is treated as having a higher priority. Specified by BG_PRIORITY(priority).
• Tile -- Tile Base Offset -- Selects which address range of memory will contain tile data. There are sixteen blocks of memory to store tile data. Each block is 0x4000 bytes (16384 bytes, or 16kb) long. See Background Tile/Map Addresses for a layout of the memory blocks. Specified by BG_TILE_RAM(base_offset).
• Mosiac --
• Color -- Number of Colors -- Specifies the size of the color palette. A value of 1 indicates 256 color mode, and a value of 0 indicates 16 color mode. This impacts the layout of the tile. 256 color requires a 1 byte index into the palette, while 16 color requires a 1 nibble (two nibbles per byte) index, packig the tile description into half of the space. 16 color tiles are not available with rotation backgrounds (Rotation Backgrounds.) Can be either BG_256_COLOR or BG_16_COLOR.
• Map -- Map Base Offset -- Select which address range of memory will contain tile data. There are 32 blocks of memory to store map data. Each block is 0x800 bytes (2048 bytes, or 2kb) long. See Background Tile/Map Addresses for a layout of the memory blocks. Specified by BG_MAP_RAM(base_offset).
• Wrap -- Background Wrap -- Only applies to rotation backgrounds (Rotation Backgrounds.) Setting the bit to 1 enables wrapping of the background while specifying a value of 0 disables wrapping of the background. Specified by BG_WRAP_ON or BG_WRAP_OFF.
• Size -- Map Size -- Determines the size of the map. Each block of map memory provides enough memory for a 32 tile x 32 tile map. See Background Map Sizes for a description of the tile size of each map based on the type of map, and the settings for these bits.

Background Tile/Map Addresses

Care must be taken in choosing the map and graphic addresses as they overlap.

Address	Map Addresses	Graphic Addresses
0x06000000	BG_MAP_RAM(0)	BG_TILE_RAM(0)
0x06000800	BG_MAP_RAM(1)
0x06001000	BG_MAP_RAM(2)
0x06001800	BG_MAP_RAM(3)
0x06002000	BG_MAP_RAM(4)
0x06002800	BG_MAP_RAM(5)
0x06003000	BG_MAP_RAM(6)
0x06003800	BG_MAP_RAM(7)
0x06004000	BG_MAP_RAM(8)	BG_TILE_RAM(1)
0x06004800	BG_MAP_RAM(9)
0x06005000	BG_MAP_RAM(10)
0x06005800	BG_MAP_RAM(11)
0x06006000	BG_MAP_RAM(12)
0x06006800	BG_MAP_RAM(13)
0x06007000	BG_MAP_RAM(14)
0x06007800	BG_MAP_RAM(15)
0x06008000	BG_MAP_RAM(16)	BG_TILE_RAM(2)
0x06008800	BG_MAP_RAM(17)
0x06009000	BG_MAP_RAM(18)
0x06009800	BG_MAP_RAM(19)
0x0600A000	BG_MAP_RAM(20)
0x0600A800	BG_MAP_RAM(21)
0x0600B000	BG_MAP_RAM(22)
0x0600B800	BG_MAP_RAM(23)
0x0600C000	BG_MAP_RAM(24)	BG_TILE_RAM(3)
0x0600C800	BG_MAP_RAM(25)
0x0600D000	BG_MAP_RAM(26)
0x0600D800	BG_MAP_RAM(27)
0x0600E000	BG_MAP_RAM(28)
0x0600E800	BG_MAP_RAM(29)
0x0600F000	BG_MAP_RAM(30)
0x0600F800	BG_MAP_RAM(31)

Background Map Sizes

Backgrounds are be larger than the screen. To specify which portion of the map to display, use the BG0_X0 (0x04000010) and BG0_Y0 (0x04000012) registers to specify the upper left position within the map. See Tile Overview for more details.

Size Setting	Text Background Size in Pixels (Tiles)	Rotational Background Size in Pixels (Tiles)
0	256x256 (32x32)	128x128 (16x16)
1	256x512 (32x64)	256x256 (32x32)
2	512x256 (64x32)	512x512 (64x64)
3	512x512 (64x64)	1024x1024 (128x128)

BG0_X0 (0x04000010)

BG0_Y0 (0x04000012)

SUB_BG0_CR (0x04001008)

This 16 bit register controls the features related to background #0 on the main display. To activate this register, this background must be enabled in the SUB_DISPLAY_CR (0x04001000).

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Size		Wrap	Map					Color	Mosaic	U	U	Tile		Pri

For a detailed description of the attributes other than Map and Tile, see BG0_CR (0x04000008). Map and tile work the same as for BG0_CR (0x04000008), but the address that the offsets represent are different.

Background Tile/Map Addresses

Care must be taken in choosing the map and graphic addresses as they overlap.

Address	Map Addresses	Graphic Addresses
0x06200000	BG_MAP_RAM(0)	BG_TILE_RAM(0)
0x06200800	BG_MAP_RAM(1)
0x06201000	BG_MAP_RAM(2)
0x06201800	BG_MAP_RAM(3)
0x06202000	BG_MAP_RAM(4)
0x06202800	BG_MAP_RAM(5)
0x06203000	BG_MAP_RAM(6)
0x06203800	BG_MAP_RAM(7)
0x06204000	BG_MAP_RAM(8)	BG_TILE_RAM(1)
0x06204800	BG_MAP_RAM(9)
0x06205000	BG_MAP_RAM(10)
0x06205800	BG_MAP_RAM(11)
0x06206000	BG_MAP_RAM(12)
0x06206800	BG_MAP_RAM(13)
0x06207000	BG_MAP_RAM(14)
0x06207800	BG_MAP_RAM(15)
0x06208000	BG_MAP_RAM(16)	BG_TILE_RAM(2)
0x06208800	BG_MAP_RAM(17)
0x06209000	BG_MAP_RAM(18)
0x06209800	BG_MAP_RAM(19)
0x0620A000	BG_MAP_RAM(20)
0x0620A800	BG_MAP_RAM(21)
0x0620B000	BG_MAP_RAM(22)
0x0620B800	BG_MAP_RAM(23)
0x0620C000	BG_MAP_RAM(24)	BG_TILE_RAM(3)
0x0620C800	BG_MAP_RAM(25)
0x0620D000	BG_MAP_RAM(26)
0x0620D800	BG_MAP_RAM(27)
0x0620E000	BG_MAP_RAM(28)
0x0620E800	BG_MAP_RAM(29)
0x0620F000	BG_MAP_RAM(30)
0x0620F800	BG_MAP_RAM(31)

SUB_BG0_X0 (0x04001010)

SUB_BG0_Y0 (0x04001012)

BG1_CR (0x0400000A)

This 16 bit register controls the features related to background #1 on the main display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

BG1_X0 (0x04000014)

This 16 bit register controls the X index into the map area to be display on the main screen. The capabilities and settings for this register is identical to BG0_X0 (0x04000010).

BG1_Y0 (0x04000016)

This 16 bit register controls the Y index into the map area to be display on the main screen. The capabilities and settings for this register is identical to BG0_Y0 (0x04000012).

SUB_BG1_CR (0x0400100A)

This 16 bit register controls the features related to background #1 on the top display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

SUB_BG1_X0 (0x04001014)

This 16 bit register controls the X index into the map area to be display on the top screen. The capabilities and settings for this register is identical to SUB_BG0_X0 (0x04001010).

SUB_BG1_Y0 (0x04001016)

This 16 bit register controls the Y index into the map area to be display on the top screen. The capabilities and settings for this register is identical to SUB_BG0_X0 (0x04001010).

BG2_CR (0x0400000C)

This 16 bit register controls the features related to background #2 on the main display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

BG2_X0 (0x04000018)

BG2_Y0 (0x0400001A)

BG2_XDX (0x04000020)

BG2_XDY (0x04000022)

BG2_YDX (0x04000024)

BG2_YDY (0x04000026)

BG2_CX (0x04000028)

BG2_CY 0x0400002C)

BG3_XDX (0x04000030)

BG3_XDY (0x04000032)

BG3_YDX (0x04000034)

BG3_YDY (0x04000036)

BG3_CX (0x04000038)

BG3_CY (0x0400003C)

SUB_BG2_CR (0x0400100C)

This 16 bit register controls the features related to background #2 on the top display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

SUB_BG2_X0 (0x04001018)

SUB_BG2_Y0 (0x0400101A)

SUB_BG2_XDX (0x04001020)

SUB_BG2_XDY (0x04001022)

SUB_BG2_YDX (0x04001024)

SUB_BG2_YDY (0x04001026)

SUB_BG2_CX (0x04001028)

SUB_BG2_CY (0x0400102C)

BG3_CR (0x0x0400000E)

This 16 bit register controls the features related to background #3 on the main display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

BG3_X0 (0x0400001C)

BG3_Y0 (0x0400001E)

SUB_BG3_CR (0x0400100E)

This 16 bit register controls the features related to background #3 on the top display. The capabilities and settings for this register is identical to BG0_CR (0x04000008).

SUB_BG3_X0 (0x0400101C)

SUB_BG3_Y0 (0x0400101E)

SUB_BG3_XDX (0x04001030)

SUB_BG3_XDY (0x04001032)

SUB_BG3_YDX (0x04001034)

SUB_BG3_YDY (0x04001036)

SUB_BG3_CX (0x04001038)

SUB_BG3_CY (0x0400103C)

IME

IRQ_HANDLER

IE

IF

DISP_SR

SCHANNEL_CR(0) (0x04000400)

SCHANNEL_SOURCE(0) (0x04000404)

SCHANNEL_TIMER(0) (0x04000408)

SCHANNEL_REPEAT_POINT(0) (0x0400040A)

SCHANNEL_LENGTH(0) (0x0400040C)

SCHANNEL_CR(1) (0x04000410)

SCHANNEL_SOURCE(1) (0x04000414)

SCHANNEL_TIMER(1) (0x04000418)

SCHANNEL_REPEAT_POINT(1) (0x0400041A)

SCHANNEL_LENGTH(1) (0x0400041C)

SCHANNEL_CR(2) (0x04000420)

SCHANNEL_SOURCE(2) (0x04000424)

SCHANNEL_TIMER(2) (0x04000428)

SCHANNEL_REPEAT_POINT(2) (0x0400042A)

SCHANNEL_LENGTH(2) (0x0400042C)

SCHANNEL_CR(3) (0x04000430)

SCHANNEL_SOURCE(3) (0x04000434)

SCHANNEL_TIMER(3) (0x04000438)

SCHANNEL_REPEAT_POINT(3) (0x0400043A)

SCHANNEL_LENGTH(3) (0x0400043C)

SCHANNEL_CR(4) (0x04000440)

SCHANNEL_SOURCE(4) (0x04000444)

SCHANNEL_TIMER(4) (0x04000448)

SCHANNEL_REPEAT_POINT(4) (0x0400044A)

SCHANNEL_LENGTH(4) (0x0400044C)

SCHANNEL_CR(5) (0x04000450)

SCHANNEL_SOURCE(5) (0x04000454)

SCHANNEL_TIMER(5) (0x04000458)

SCHANNEL_REPEAT_POINT(5) (0x0400045A)

SCHANNEL_LENGTH(5) (0x0400045C)

SCHANNEL_CR(6) (0x04000460)

SCHANNEL_SOURCE(6) (0x04000464)

SCHANNEL_TIMER(6) (0x04000468)

SCHANNEL_REPEAT_POINT(6) (0x0400046A)

SCHANNEL_LENGTH(6) (0x0400046C)

SCHANNEL_CR(7) (0x04000470)

SCHANNEL_SOURCE(7) (0x04000474)

SCHANNEL_TIMER(7) (0x04000478)

SCHANNEL_REPEAT_POINT(7) (0x0400047A)

SCHANNEL_LENGTH(7) (0x0400047C)

SCHANNEL_CR(8) (0x04000480)

SCHANNEL_SOURCE(8) (0x04000484)

SCHANNEL_TIMER(8) (0x04000488)

SCHANNEL_REPEAT_POINT(8) (0x0400048A)

SCHANNEL_LENGTH(8) (0x0400048C)

SCHANNEL_CR(9) (0x04000490)

SCHANNEL_SOURCE(9) (0x04000494)

SCHANNEL_TIMER(9) (0x04000498)

SCHANNEL_REPEAT_POINT(9) (0x0400049A)

SCHANNEL_LENGTH(9) (0x0400049C)

SCHANNEL_CR(10) (0x040004A0)

SCHANNEL_SOURCE(10) (0x040004A4)

SCHANNEL_TIMER(10) (0x040004A8)

SCHANNEL_REPEAT_POINT(10) (0x040004AA)

SCHANNEL_LENGTH(10) (0x040004AC)

SCHANNEL_CR(11) (0x040004B0)

SCHANNEL_SOURCE(11) (0x040004B4)

SCHANNEL_TIMER(11) (0x040004B8)

SCHANNEL_REPEAT_POINT(11) (0x040004BA)

SCHANNEL_LENGTH(11) (0x040004BC)

SCHANNEL_CR(12) (0x040004C0)

SCHANNEL_SOURCE(12) (0x040004C4)

SCHANNEL_TIMER(12) (0x040004C8)

SCHANNEL_REPEAT_POINT(12) (0x040004CA)

SCHANNEL_LENGTH(12) (0x040004CC)

SCHANNEL_CR(13) (0x040004D0)

SCHANNEL_SOURCE(13) (0x040004D4)

SCHANNEL_TIMER(13) (0x040004D8)

SCHANNEL_REPEAT_POINT(13) (0x040004DA)

SCHANNEL_LENGTH(13) (0x040004DC)

SCHANNEL_CR(14) (0x040004E0)

SCHANNEL_SOURCE(14) (0x040004E4)

SCHANNEL_TIMER(14) (0x040004E8)

SCHANNEL_REPEAT_POINT(14) (0x040004EA)

SCHANNEL_LENGTH(14) (0x040004EC)

SCHANNEL_CR(15) (0x040004F0)

SCHANNEL_SOURCE(15) (0x040004F4)

SCHANNEL_TIMER(15) (0x040004F8)

SCHANNEL_REPEAT_POINT(15) (0x040004FA)

SCHANNEL_LENGTH(15) (0x040004FC)

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